1. Field of the Invention
The present invention relates to high density integrated circuit devices, and more particularly to interconnect structures for multi-level three-dimensional stacked devices.
2. Description of Related Art
In three-dimensional (3D) stacked memory devices, multi-level vertical plugs are used to couple multiple layers of memory cells to decoding circuitry. Z-direction decoding (“Z-decoding”) in 3D memory devices can be challenging. Methods such as minimal incremental layer cost (MiLC) are complicated and expensive. Methods such as direct vertical plug landing on multi-layers are straightforward for Z-decoding. However, they decrease the process window as the number of layers increase, because the depth difference between top and bottom layers may be larger than several hundreds to several thousands of nanometers.
It is desirable to provide a method for Z-decoding in 3D memory manufacturing that enlarges the process window as compared to existing technologies.